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contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, fo r any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor device s when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate ( board or glass) or product design stage. 2. always test and inspect products under the env ironment with no penetration of light. s 6b1 71 3 65 com / 1 32 seg driver & controller for stn lcd march . 2002 ver. 4.2
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 2 s6b1713 specification revision history version content date 2.0 neglect the more past version than version 2.0 nov. 1998 2.1 f osc = 16kh z (typ.) ? 22khz (typ.): for removing flicker phenomenon temperature coefficient (when temps = l): - 0.0%/ c ? - 0.05%/ c nov. 1998 3.0 modified some syntax errors voltage regulator reference voltage [v ref ]: tbd ? 2.0 modified voltage regulator block of ?fun ctional description? nov. 1998 3.1 v lcd absolute maximum rating: 15.0v ? 17.0v power consumption: 100 m a ? 80 m a 3.2 oscillator frequency (1): 19 ( m in.) ? 17 ( m in.), 25 ( m ax.) ? 27 (m ax.) oscillator frequency (2): 22 ( m in.) ? 20 ( m in.), 28 ( m ax.) ? 30 ( m ax.) 3.3 modified y - axis values of ?pad center coordinates? modified the contents of ?referential instruction setup flow? 3.4 word - processor version change apr.1999 3.5 modified error: pad no.113 (coms) y coordinate: - 1210 ? - 1140 (after) oct.1999 4.0 chan ge vdd range : 2.4v to 5.5v ? 2.4v to 3.6v jan.2000 4.1 added detail information for several items mar.2001 4.2 change vdd range : 2.4v to 3.6v ? 2.4v to 5.5v mar.2002
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 block diagram ................................ ................................ ................................ ................................ ......... 3 pad configuration ................................ ................................ ................................ ................................ . 4 pad center coordinat es ................................ ................................ ................................ ...................... 5 pin description ................................ ................................ ................................ ................................ ........ 8 power supply ................................ ................................ ................................ ................................ .... 8 lcd driver supply ................................ ................................ ................................ ............................ 8 system control ................................ ................................ ................................ ................................ 9 microprocessor inter face ................................ ................................ ................................ ......... 11 lcd driver outputs ................................ ................................ ................................ ......................... 13 functional descri ption ................................ ................................ ................................ ....................... 14 microprocessor inter face ................................ ................................ ................................ ......... 14 display data ram (dd ram) ................................ ................................ ................................ .............. 18 lcd display circuits ................................ ................................ ................................ ....................... 21 lcd driver circuit ................................ ................................ ................................ ........................... 23 power supply circuit s ................................ ................................ ................................ .................. 24 referece circuit exa mples ................................ ................................ ................................ .......... 31 reset circuit ................................ ................................ ................................ ................................ .... 33 instruction descript ion ................................ ................................ ................................ ...................... 34 specifications ................................ ................................ ................................ ................................ ......... 48 absolute maximum rat ings ................................ ................................ ................................ ........... 48 dc characteristics ................................ ................................ ................................ ........................ 49 reference data ................................ ................................ ................................ ............................... 52 ac characteristics ................................ ................................ ................................ ......................... 54 reference applicatio ns ................................ ................................ ................................ ...................... 60 microprocessor inter face ................................ ................................ ................................ ......... 60 connections between s6b1713 and lcd pane l ................................ ................................ ......... 61 tcp pin layout (samp le) ................................ ................................ ................................ .................. 66

s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 1 introduction the s6b1713 is a driver & controller lsi for graphic dot - matrix liquid crystal display systems. it contains 6 5 common s and 1 32 segment s driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8 - bit parallel display data and stores in an on - chip d ispl ay d ata ram of 65 x 1 32 bits. it provides a high - flexible display section due to 1 - to - 1 correspondence between on - chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no externally operating clock to m inimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 6 5 common outputs / 1 32 segment outpu ts on - chip display data ram - capacity: 65 x 1 32 = 8 , 58 0 bits applicable duty ratios d uty ratio applicable lcd bias maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 1 32 1/49 1/6 or 1/8 49 132 1/33 1/5 or 1/6 33 132 microprocessor interface - 8 - bit paral lel bi - directional interface with 6800 - series or 8080 - series - serial interface (only write operation) available function set - various i nstructions s ets - h/w, s/w r eset capable built - in a nalog c ircuit - on - chip oscillator circuit - voltage converter (x2 , x3, x4, x5) - voltage regulator ( t emperature coefficient: - 0.05%/ c , - 0. 2 %/ c) - voltage follower - e lectronic contrast control function (64 steps) operating voltage range - s upply voltage 2 (v dd ): 2.4 to 5.5 v - lcd driving voltage (v lcd = v0 - v ss ): 4. 0 to 1 5 .0 v low power consumption - 70 m a typ. (v dd = 3v, x 4 boosting, v0 = 1 1 v, internal power supply on) - 10 m a max. (during power save [standby] mode) package type - gold bumped chip or tcp
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 2 series specifications product c ode temps pin temperature c oeff icient package type chip t hickness s6b1713a05 - b0cz 670 m m s6b1713a05 - b0cy 0 (v ss c onnected) - 0.05%/ c 470 m m s6b1713a15 - b0cz 670 m m s6b1713a15 - b0cy 1 (v dd c onnected) - 0.2%/ c cog 470 m m s6b1713a05 - xxx0 670 m m s6 b1713a05 - xxxn 0 (v ss c onnected) - 0.05%/ c 470 m m s6b1713a15 - xxx0 670 m m s6b1713a15 - xxxn 1 (v dd c onnected) - 0.2%/ c tcp 470 m m * xx: tcp ordering number
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 3 block diagram ms cl m frs disp duty0 duty1 vdd v0 v1 v2 v3 v4 vss hpmb v0 vr intrs te mps vout c1- c1+ c2- c2+ c3 - c 3+ dcdc5b bsts v / c circuit v / r circuit v / f circuit 33 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line address circuit page address circuit display data ram 65 x 1 32 = 8 , 58 0 bits segment controller display timing generator circuit common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) mi resetb p s rw_wr e_rd r s c s2 cs1b coms com64 : com33 seg132 seg131 seg130 : : seg3 seg2 seg1 com32 : com1 coms oscillator 1 32 segment driver circuits 33 common driver circuits i/o buffer status register instruction register cls figure 1 . block diagram
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 4 pad configuration eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 1 48 2 87 1 47 2 88 11 1 32 4 11 0 1 s 6b1 71 3 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eee eeee - - - - eee figure 2 . s6b1713 chip configuration table 1 . s6b1713 pad dimensions size items pad no. x y unit chip size - 10860 2 92 0 1 to 110 90 pad pitch 11 1 to 32 4 7 0 1 to 110 5 6 11 4 11 1 to 1 47 108 50 1 48 to 2 87 50 108 bumped pad size 2 88 to 32 4 108 50 bumped pad height 1 to 32 4 1 7 (typ.) m m figure 3. cog align key coordinate figure 4. ilb align key coordinate (with gold bump *) 30 m m 30 m m 30 m m (-5065, +1302) 30 m m 30 m m 30 m m (+5065, +1317) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-5060, -1180) (+5060, -1180) 42 m m 108 m m * when designing electrode pattern must be prohibited on this area ( ilb align key ). if electrode pattern is used for routing over this area, it can be happened pattern - short through gold bump pattern on ilb align key .
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 5 pad center coordinates table 2 . p ad center coordinates [unit: m m] no. name x y no. name x y no. name x y 1 dummy -4905 -1336 51 vdd -405 -1336 101 bsts 4095 -1336 2 dummy -4815 -1336 52 vdd -315 -1336 102 dcdc5b 4185 -1336 3 frs -4725 -1336 53 vdd -225 -1336 103 vdd 4275 -1336 4 m -4635 -1336 54 vdd -135 -1336 104 hpm 4365 -1336 5 cl -4545 -1336 55 vdd -45 -1336 105 intrs 4455 -1336 6 disp -4455 -1336 56 vdd 45 -1336 106 vss 4545 -1336 7 vss -4365 -1336 57 vout 135 -1336 107 temps 4635 -1336 8 cs1b -4275 -1336 58 vout 225 -1336 108 vdd 4725 -1336 9 cs2 -4185 -1336 59 vout 315 -1336 109 dummy 4815 -1336 10 vdd -4095 -1336 60 vout 405 -1336 110 dummy 4905 -1336 11 resetb -4005 -1336 61 c3+ 495 -1336 111 dummy 5271 -1280 12 rs -3915 -1336 62 c3+ 585 -1336 112 dummy 5271 -1210 13 vss -3825 -1336 63 c3+ 675 -1336 113 coms 5271 -1140 14 rw_wr -3735 -1336 64 c3+ 765 -1336 114 com1 5271 -1070 15 e_rd -3645 -1336 65 c3- 855 -1336 115 com2 5271 -1000 16 vdd -3555 -1336 66 c3- 945 -1336 116 com3 5271 -930 17 db0 -3465 -1336 67 c3- 1035 -1336 117 com4 5271 -860 18 db1 -3375 -1336 68 c3- 1125 -1336 118 com5 5271 -790 19 db2 -3285 -1336 69 c1+ 1215 -1336 119 com6 5271 -720 20 db3 -3195 -1336 70 c1+ 1305 -1336 120 com7 5271 -650 21 db4 -3105 -1336 71 c1+ 1395 -1336 121 com8 5271 -580 22 db5 -3015 -1336 72 c1+ 1485 -1336 122 com9 5271 -510 23 db6 -2925 -1336 73 c1- 1575 -1336 123 com10 5271 -440 24 db7 -2835 -1336 74 c1- 1665 -1336 124 com11 5271 -370 25 vss -2745 -1336 75 c1- 1755 -1336 125 com12 5271 -300 26 vdd -2655 -1336 76 c1- 1845 -1336 126 com13 5271 -230 27 vdd -2565 -1336 77 c2+ 1935 -1336 127 com14 5271 -160 28 vdd -2475 -1336 78 c2+ 2025 -1336 128 com15 5271 -90 29 duty0 -2385 -1336 79 c2+ 2115 -1336 129 com16 5271 -20 30 duty1 -2295 -1336 80 c2+ 2205 -1336 130 com17 5271 50 31 vss -2205 -1336 81 c2- 2295 -1336 131 com18 5271 120 32 ms -2115 -1336 82 c2- 2385 -1336 132 com19 5271 190 33 cls -2025 -1336 83 c2- 2475 -1336 133 com20 5271 260 34 vdd -1935 -1336 84 c2- 2565 -1336 134 com21 5271 330 35 mi -1845 -1336 85 vss 2655 -1336 135 com22 5271 400 36 ps -1755 -1336 86 vss 2745 -1336 136 com23 5271 470 37 vss -1665 -1336 87 vr 2835 -1336 137 com24 5271 540 38 vss -1575 -1336 88 vr 2925 -1336 138 com25 5271 610 39 vss -1485 -1336 89 v0 3015 -1336 139 com26 5271 680 40 vss -1395 -1336 90 v0 3105 -1336 140 com27 5271 750 41 vss -1305 -1336 91 v1 3195 -1336 141 com28 5271 820 42 vss -1215 -1336 92 v1 3285 -1336 142 com29 5271 890 43 vss -1125 -1336 93 v2 3375 -1336 143 com30 5271 960 44 vss -1035 -1336 94 v2 3465 -1336 144 com31 5271 1030 45 vss -945 -1336 95 v3 3555 -1336 145 com32 5271 1100 46 vss -855 -1336 96 v3 3645 -1336 146 dummy 5271 1170 47 vdd -765 -1336 97 v4 3735 -1336 147 dummy 5271 1240 48 vdd -675 -1336 98 v4 3825 -1336 148 dummy 4865 1301 49 vdd -585 -1336 99 vss 3915 -1336 149 dummy 4795 1301 50 vdd -495 -1336 100 vss 4005 -1336 150 dummy 4725 1301
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 6 table 2 . p ad center coordinates (continued) [unit: m m] no. name x y no. name x y no. name x y 151 dummy 4655 1301 201 seg50 1155 1301 251 seg100 -2345 1301 152 seg1 4585 1301 202 seg51 1085 1301 252 seg101 -2415 1301 153 seg2 4515 1301 203 seg52 1015 1301 253 seg102 -2485 1301 154 seg3 4445 1301 204 seg53 945 1301 254 seg103 -2555 1301 155 seg4 4375 1301 205 seg54 875 1301 255 seg104 -2625 1301 156 seg5 4305 1301 206 seg55 805 1301 256 seg105 -2695 1301 157 seg6 4235 1301 207 seg56 735 1301 257 seg106 -2765 1301 158 seg7 4165 1301 208 seg57 665 1301 258 seg107 -2835 1301 159 seg8 4095 1301 209 seg58 595 1301 259 seg108 -2905 1301 160 seg9 4025 1301 210 seg59 525 1301 260 seg109 -2975 1301 161 seg10 3955 1301 211 seg60 455 1301 261 seg110 -3045 1301 162 seg11 3885 1301 212 seg61 385 1301 262 seg111 -3115 1301 163 seg12 3815 1301 213 seg62 315 1301 263 seg112 -3185 1301 164 seg13 3745 1301 214 seg63 245 1301 264 seg113 -3255 1301 165 seg14 3675 1301 215 seg64 175 1301 265 seg114 -3325 1301 166 seg15 3605 1301 216 seg65 105 1301 266 seg115 -3395 1301 167 seg16 3535 1301 217 seg66 35 1301 267 seg116 -3465 1301 168 seg17 3465 1301 218 seg67 -35 1301 268 seg117 -3535 1301 169 seg18 3395 1301 219 seg68 -105 1301 269 seg118 -3605 1301 170 seg19 3325 1301 220 seg69 -175 1301 270 seg119 -3675 1301 171 seg20 3255 1301 221 seg70 -245 1301 271 seg120 -3745 1301 172 seg21 3185 1301 222 seg71 -315 1301 272 seg121 -3815 1301 173 seg22 3115 1301 223 seg72 -385 1301 273 seg122 -3885 1301 174 seg23 3045 1301 224 seg73 -455 1301 274 seg123 -3955 1301 175 seg24 2975 1301 225 seg74 -525 1301 275 seg124 -4025 1301 176 seg25 2905 1301 226 seg75 -595 1301 276 seg125 -4095 1301 177 seg26 2835 1301 227 seg76 -665 1301 277 seg126 -4165 1301 178 seg27 2765 1301 228 seg77 -735 1301 278 seg127 -4235 1301 179 seg28 2695 1301 229 seg78 -805 1301 279 seg128 -4305 1301 180 seg29 2625 1301 230 seg79 -875 1301 280 seg129 -4375 1301 181 seg30 2555 1301 231 seg80 -945 1301 281 seg130 -4445 1301 182 seg31 2485 1301 232 seg81 -1015 1301 282 seg131 -4515 1301 183 seg32 2415 1301 233 seg82 -1085 1301 283 seg132 -4585 1301 184 seg33 2345 1301 234 seg83 -1155 1301 284 dummy -4655 1301 185 seg34 2275 1301 235 seg84 -1225 1301 285 dummy -4725 1301 186 seg35 2205 1301 236 seg85 -1295 1301 286 dummy -4795 1301 187 seg36 2135 1301 237 seg86 -1365 1301 287 dummy -4865 1301 188 seg37 2065 1301 238 seg87 -1435 1301 288 dummy -5271 1240 189 seg38 1995 1301 239 seg88 -1505 1301 289 dummy -5271 1170 190 seg39 1925 1301 240 seg89 -1575 1301 290 coms -5271 1100 191 seg40 1855 1301 241 seg90 -1645 1301 291 com64 -5271 1030 192 seg41 1785 1301 242 seg91 -1715 1301 292 com63 -5271 960 193 seg42 1715 1301 243 seg92 -1785 1301 293 com62 -5271 890 194 seg43 1645 1301 244 seg93 -1855 1301 294 com61 -5271 820 195 seg44 1575 1301 245 seg94 -1925 1301 295 com60 -5271 750 196 seg45 1505 1301 246 seg95 -1995 1301 296 com59 -5271 680 197 seg46 1435 1301 247 seg96 -2065 1301 297 com58 -5271 610 198 seg47 1365 1301 248 seg97 -2135 1301 298 com57 -5271 540 199 seg48 1295 1301 249 seg98 -2205 1301 299 com56 -5271 470 200 seg49 1225 1301 250 seg99 -2275 1301 300 com55 -5271 400
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 7 table 2. p ad center coordinates (continued) [unit: m m] no. name x y no. name x y no. name x y 301 com54 -5271 330 302 com53 -5271 260 303 com52 -5271 190 304 com51 -5271 120 305 com50 -5271 50 306 com49 -5271 -20 307 com48 -5271 -90 308 com47 -5271 -160 309 com46 -5271 -230 310 com45 -5271 -300 311 com44 -5271 -370 312 com43 -5271 -440 313 com42 -5271 -510 314 com41 -5271 -580 315 com40 -5271 -650 316 com39 -5271 -720 317 com38 -5271 -790 318 com37 -5271 -860 319 com36 -5271 -930 320 com35 -5271 -1000 321 com34 -5271 -1070 322 com33 -5271 -1140 323 dummy -5271 -1210 324 dummy -5271 -1280
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 8 pin description power su pply table 3. power supply pin description name i/o description vdd supply power supply v ss supply ground lcd driver supply voltages the voltage determined by lcd pixel is impedance - converted by an operational amplifier for applicati on. voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/ 9 bia s ( 8/9 ) x v0 ( 7/9 ) x v0 ( 2/9 ) x v0 ( 1/9 ) x v0 1/ 8 bias (7 / 8) x v0 ( 6/ 8) x v0 ( 2/8 ) x v0 ( 1/8 ) x v0 1/ 7 bias (6 / 7) x v0 (5/ 7 ) x v0 ( 2/7 ) x v0 ( 1/7 ) x v0 1/ 6 bias (5 / 6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/6 ) x v0 1/ 5 bias (4 / 5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/5 ) x v0 v0 v1 v2 v3 v4 i/o lcd driver supply table 4. lcd driver supply pin description name i/o description c1 - o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2 - o capacitor 2 negat ive connection pin for voltage converter c2+ o capacitor 2 positive connection pin for voltage converter c3 - o capacitor 3 negative connection pin for voltage converter c 3 + o capacitor 3 positive connection pin for voltage converter vout i/o voltage co nverter input / output pin dcdc5b i 5 times boosting circuit enable input pin when this pin is low in 4 times boosting circuit, the 5 - times boosting voltage appears at vout. vr i v0 voltage adjustment pin it is valid only when on - chip resistors are not used (intrs = ?l?) .
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 9 system control table 5. system control pin description name i/o description master / slave operation select pin - ms = "h": master operation - ms = "l": slave operation the following table depends on the ms status. ms cls osc c ircuit power s upply c ircuit cl m frs disp h enabled enabled output output output output h l disabled enabled input output output output l h or l disabled disabled input input output input ms i when slave mode, the cls pin must be fixed ? h ? or ? l ? cl s i built - in oscillator circuit enable / disable select pin - cls = ? h ? : e nable - cls = ? l ? : d isable ( e xternal display clock input to cl pin) cl i/o display clock input / output pin when the s6b1713 is used in master/slave mode (multi - chip), the cl pi ns must be connected each other. m i/o lcd ac signal input / output pin when the s6b1713 is used in master/slave mode (multi - chip), the m pins must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput frs o static driver segment output pin this pin is used together with the m pin. disp i/o lcd display blanking control input / output when s6b1713 is used in master/slave mode (multi - chip), the disp pins must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput intrs i internal resistors select pin this pin selects the resistors for adjusting v0 voltage level. - intrs = "h": use the internal resistors. - intrs = "l": use the external resistors. v0 voltage is controlled with vr pin and external resistive divider. hpm i power control pin of the power supply circuit for lcd driver - hpm = " h ": high power mode - hpm = " l ": normal mode this pin is valid in master operation. temps i selects temperature coefficient of the reference voltage - temps = " l ": - 0.05%/ c - temps = " h ": - 0.2%/ c
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 10 table 5. system control pin description (continued) name i/o description selects input voltages of the built - in v oltage converter bsts voltage c onverter i nput voltage r emarks l 4v v dd > 4v h v dd 2.4v v dd 5.5v bsts i note: because the maximum vo ltage of v dd has been changed to 5.5v, we strongly recommend that bsts pin should be fixed to ? h ? . the lcd driver duty ratio depends on the following table d uty 1 d uty 0 duty r atio l l 1/33 l h 1/49 h l/h 1/65 d uty 0 d uty 1 i
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 11 microprocessor inter face table 6. microprocessor i nterface pin description name i/o description resetb i reset input pin when resetb is ?l?, initialization is executed. parallel / serial data input select input ps interface mode chip s elect data / instruction data read / write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rd rw_wr - l serial cs1b, cs2 rs sid(db7) write only sclk(db6) ps i *note: in serial mode , it is impossible to read data from the on - chip ram. and db0 to db5 are high imp edance and e_rd and rw_wr must be fixed to either ?h? or ?l?. mi i microprocessor interface selects input pin - mi = "h": 6800 - series mpu interface - mi = "l": 8080 - series mpu interface cs1b cs2 i chip select input pins data / instruction i/o is enabled only when cs1b is ?l? and cs2 is ?h?. when chip select is non - active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin mi mpu type rw_wr description h 6800 - series rw read / write control input pin - rw = ?h?: r ead - rw = ?l?: w rite l 8080 - series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 12 tab le 6. microprocessor interface pin description (continued) name i/o description read / write execution control pin mi mpu type e_rd description h 6800 - series e read / write control input pin - rw = ?h?: when e is ?h?, db0 to db7 are in an out put status. - rw = ?l?: the data on db0 to db7 are latched at the falling edge of the e signal. l 8080 - series /rd read enable clock input pin when /rd is ?l?, db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8 - bit bi - directional data bus that is connected to the standard 8 - bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high im pedance.
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 13 lcd driver outputs table 7. lcd driver outputs pin description name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver out put voltage display data m normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg 1 to seg 132 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common dri ver. scan data m common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com 1 to com 64 o coms o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. in multi - chip (master / slave) mode, all coms pins on both master and slave units are the same signal. note: dummy - these pins should be opened (floated).
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 14 functional descripti on microprocessor inter face chip select input there are cs1b and cs2 pins for c hip s electio n. the s6b1713 can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface s6b1713 has three types of interface with an mpu, which are one serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table 8. table 8 . parallel / serial interface mode ps type cs1b cs2 mi interface mode h 6800 - series mpu mode h parallel cs1b cs2 l 8080 - series mpu mode l serial cs1b cs2 * serial - mode * : don't care parallel interface (ps = "h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by mi as shown in table 9 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table10 . table 9 . microprocessor selection for parallel interface mi cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800 - series l cs1b cs2 rs /rd /wr db0 to db7 8080 - series table 10 . parallel data transfer common 6800 - series 8080 - series rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 15 cs1b cs2 rs rw e db command write data w rite status read data read figure 5. 6800 - series mpu interface protocol (ps= ? h ? , mi= ? h ? ) cs1b cs2 rs /wr /rd db command write data w rite status read data read figure 6. 8080 - series mpu interface protocol (ps= ? h ? , mi= ? l ? ) serial interface (ps = "l" , mi= ? h ? or ? l ?) when the s6b1713 is active, serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8 - bit shift register and the 3 - bit counter are reset. serial data can be read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 16 cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 7 . serial interface timing busy flag the b usy f lag indicates whethe r the s6b1713 is operating or not. when db7 is ?h? in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance. data transfer the s6b1713 uses bus holder and internal data bus for d ata t ransfer with the mpu. when writing data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 8 . and when reading data from on - chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 9 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 8 . write timing
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 17 rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+2) figure 9 . read timing
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 18 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 65 - row by 1 32 - column addressable ar ray. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 10 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com 1 - - com 2 - - com 3 - - com 4 - - com 5 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 display data ram lcd display figure 10 . ram - to - lcd data transfer page address circuit this circuit is for providing a p age a ddress to d isplay data ram shown in fig ure 12 . it incorporates 4 - bit p age a ddress register changed by only the ?set page? instruction. page a ddress 8 (db3 is ?h?, but db2, db1 and db0 are ?l?) is a special ram area for the icons and display data db0 is only valid. when page address is above 8, it is impossible to access to on - chip ram. line address circuit this circuit assigns ddram a l ine a ddress corresponding to the first line (com 1 ) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling a nd page switching without changing the contents of on - chip ram as shown in figure 12 . it incorporates 6 - bit line address register changed by only the initial display line instruction and 6 - bit counter circuit. at the beginning of each lcd frame, the conten ts of register are copied to the line counter which is increased by cl signal and generates the l ine a ddress for transferring the 1 32 - bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not ac cess l ine ad dress of icons.
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 19 column address circuit column address circuit has a 8 - bit preset counter that provides column address to the display data ram as shown in figure 12 . when set column address msb / lsb instruction is issued, 8 - bit [y 7 :y0] is upda ted. and, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non - existing address above 84 h. it is unlocked if a column address is set again by set column address msb / lsb instruction. and t he c olumn a ddress counter is independent of page address register. adc s elect instruction makes it possible to invert the relationship between the c olumn a ddress and the segment outputs . it is necessary to rewrite the display data on built - in ram after issuing adc s elect instruction. refer to the following figure 11 . seg output seg 1 seg 2 seg 3 seg 4 ... ... seg 129 seg 130 seg 131 seg 132 column address [y 7 :y0] 00h 01h 02h 03h ... ... 8 0h 8 1h 8 2h 8 3h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 11 . the relationship b etween t he column address a nd t he segment outputs segment control circuit this c ircuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 20 page0 page2 page1 page4 page3 page6 page5 page7 page8 line address com output page address db3 db0 db1 db2 data - - - - - - - - - - seg132 seg131 seg2 seg1 seg130 seg129 seg128 seg127 seg3 seg4 seg5 seg6 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 28h 27h 26h 25h 24h 23h 22h 21h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 38h 37h 36h 35h 34h 33h 32h 31h 39h 3ah 3bh 3ch 3dh 3eh 3fh com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com39 com38 com37 com36 com35 com33 com34 com32 com31 com40 com49 com48 com47 com46 com45 com43 com44 com42 com41 com50 com59 com58 com57 com56 com55 com53 com54 com52 com51 com60 com63 coms com62 com61 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 start 1/49 duty 1/33 duty com64 83 81 7f 80 7e 00 - 02 04 03 05 05 04 03 01 02 00 7e 7f 80 82 81 83 01 82 when the initial display line address is 1c[hex] figure 12 . display data ram map
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 21 lcd display circu its oscillator this is completely on - chip oscillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. * test condition: temperature: 25 c & 85 c, temps= ? l ? , no lo ad v dd vs. f osc 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] f osc [khz] 1/33 duty (25 c ) 1/49 duty (25 c ) 1/65 duty (25 c ) 1/33 duty (85 c ) 1/49 duty (85 c ) 1/65 duty (85 c ) figure 13. v dd vs. f osc display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl, generated by oscillation clock, generates the clock for the line counter and th e signal for the display data latch. the line address of on - chip ram is generated in synchronization with the display clock (cl) and the 1 32 - bit display data is latched by the display data latch circuit in synchronization with the display clock. the displ ay data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal(m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. driving 2 - frame ac driver waveform and internal timing signal are shown in f igure 14 . in a multi ple - chip configuration , the slave chip requires the m , cl and disp signals from the mast er. table 11 shows the m, cl, and disp status. table 11 . master and slave timing signal status operation mode oscillator m cl disp on (internal clock used) output output output master off (external clock used) output input output slave - input input in put
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 22 m com1 v0 v1 v2 v3 v4 v ss com2 v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss segn 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 cl figure 14 . 2 - frame ac driving waveform (duty ratio = 1/ 6 5) common output control circuit this circuit controls the relationship between the number of common output and specified duty ratio. shl select instruction specifi es the scanning direction of the common output pins . table 12. the relationship between duty ratio and common output common o utput p ins duty shl com[1:16] com[17:24] com[25:40] com[41:48] com[49:64] coms 0 com[1:16] *nc com[17:32] 1/33 1 com[32 :17] *nc com[16:1] coms 0 com[1:24] *nc com[25:48] 1/49 1 com[48:25] *nc com[24:1] coms 0 com[1:64] 1/65 1 com[64:1] coms *nc: no connection
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 23 lcd driver circuit this driver circuit is configured by 66 - c hannel common drivers (including 2 coms channels) and 1 32 - channel segment drivers. this lcd panel driver voltage depends on the combination of display data and m signal. com 1 com2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com1 1 com1 2 com1 3 com1 4 com1 5 com 16 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 seg 3 seg 2 seg 1 com 3 com 1 com 2 m v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 15 . segment and common timing
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 24 power supply circuit s the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and cont rolled by power control instruction. for details, refers to "instruction description". table 13 shows the referenced combinations in using power supply circuits. table 13 . recommended power supply combinations user setup power control (vc vr vf) v/c circu its v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the vo ltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 25 voltage converter circuits these circuits boost up the electric potential b etween v dd and v ss to 2, 3, 4 or 5 times toward positive side and boosted voltage is outputted from vout pin. [c1 = 1.0 to 4.7 m f] vout = 2 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b v dd v dd v ss v dd - + - + c1 c1 gnd v ss v dd vout = 3 v dd v dd v ss v dd v dd - + + - - + c1 c1 c1 gnd v ss v dd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b figure 16 . two times boosting circuit figure 17 . three times boo sting circuit vout = 4 v dd v dd v dd v ss - - + + - + - + c1 c1 c1 c1 gnd v ss v dd v dd v dd v dd v ss c1 + - - + - + - + c1 c1 c1 gnd v ss v dd vout = 5 v dd gnd vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b vout c3+ c3 - c2+ c2 - c1+ c1 - dcdc5b figure 18 . four times boosting circuit figure 19 . five times boosting circuit
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 26 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational - amplifier circuits shown in figure 20 , it is necessary to be applied internally or externally. for t he eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set referen ce voltage register", within the range 0 to 63. v ref voltage at ta = 25 c is shown in table 14 - 1 . rb v0 = ( 1 + ? ? ? ? ) x v ev [v] ------ (eq. 1) ra (63 - a ) v ev = ( 1 - ? ? ? ? ? ? ) x v ref [v] ------ (eq. 2) 3 00 table 14 - 1. v ref voltage at ta = 25 c temps temp. coefficient v ref [v] l - 0.05% / c 2.0 h - 0. 2 % / c 2.0 table 14 - 2. reference voltage parameter s ( a ) s v5 s v4 s v3 s v2 s v1 s v0 reference voltage p arame ter ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 27 v ev gnd ra rb v ss vr v0 vout + - figure 20 . internal v oltage r egulator c ircuit
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 28 in case of using internal resistors, ra and rb (intrs = "h") when intrs pin is ?h?, resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 15 . internal rb / ra ratio depending on 3 - bit data ( r2 r1 r0) 3 - bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1+(rb / ra) 1.90 2.19 2.55 3.02 3.61 4.35 5.29 6.48 the following figure shows v0 voltage measured by adjusting internal regulator re s ist o r ratio (rb / ra) and 6 - bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 electronic volume level v0 [v] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) figure 21 . electronic volume level
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 29 in case of using external resistors, ra and rb. (intrs = "l") when intrs pin is ?l?, it is necessary to connect external regulator resistor ra between vr and v ss , and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. m aximum current flowing ra, rb = 1 ua from eq . 1 rb 10 = ( 1 + ? ? ? ) x v ev [v] ------ (eq. 3) ra from eq. 2 (63 - 32) v ev = ( 1 - ? ? ? ? ? ? ) x 2.0 = 1. 7 9 [v] ------ (eq. 4) 3 00 from requirement 3. 10 ? ? ? ? ? ? = 1 [ua] ------ (eq. 5) ra + rb from equations eq. 3, 4 and 5 ra = 1. 7 9 [m w ] rb = 8. 2 1 [m w ] the following table shows the range of v0 depending on the above requirements. table 16. v0 d epending on electronic volume l ev el electronic volume level 0 ....... 32 ....... 63 v0 8. 83 ....... 10.00 ....... 11. 17
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 30 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4) and those output impedance are converted by the v ol tage f ollower for increasing drive capability. the following table shows the relationship between v1 to v4 level and each duty ratio. table 17. the relationship between v1 to v4 level and duty ratio duty ratio duty1 duty0 lcd bias v1 v2 v3 v4 1/5 (4/5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/ 5) x v0 1/33 l l 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/49 l h 1/8 (7/8) x v0 (6 / 8) x v0 ( 2/ 8) x v0 ( 1/ 8) x v0 1/ 7 (6/7) x v0 (5 / 7) x v0 ( 2/ 7) x v0 ( 1/ 7) x v0 1/65 h l/h 1/9 (8/9) x v0 (7 / 9) x v0 ( 2/ 9) x v0 ( 1/ 9) x v0
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 31 referece circuit exa mples ms intrs v ss c1 c2 - + c2 - + c2 - + c2 - + c2 - + v dd ms intrs v ss c1 ra rb v ss v dd vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c1 c1 c1 c1 c1 c1 when using internal regulator resistors when not using internal regulator resistors figure 22. when using all lcd power circuits (4 - time v/c: o n , v/r: on , v/f: o n ) when using internal regulator resistors when not using internal regulator resistors v dd ms intrs v ss ra rb v ss v dd ms intrs v ss external power supply external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 figure 23. when using s ome lc d power circuits (v/c: o ff , v/r: o n , v/f: o n )
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 32 ms intrs v ss c2 - + c2 - + c2 - + c2 - + c2 - + v dd vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 external power supply figure 24. when using s ome lcd power circuits (v/c: o ff , v/r: o ff , v/f: o n ) v dd ms intrs v ss external power supply vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 value of external capacitance item value unit c1 1.0 to 4.7 c2 0.47 to 1.0 m f figure 25. when not using a ny internal lcd power supply circuits (v/c: o ff , v /r: o ff , v/f: o ff )
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 33 reset circuit setting resetb to ?l? or reset instruction can initialize internal function. when resetb becomes ?l?, following procedure is occurred. display on / off: off entire display on / off: off (normal) adc select: off (normal) r everse display on / off: off (normal) power control register (vc, vr, vf) = (0, 0, 0) lcd bias ratio: 1/ 7 (1/65 d uty), 1/6 (1/49 d uty), 1/5 (1/33 d uty) r ead - m odify - write : off shl select: off (normal) static indicator mode: off static indicator register: (s 1, s0) = (0, 0) d isplay start line: 0 (first) column address: 0 page address: 0 regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) when reset instruction is issued, following procedure is occurred. r ead - m odify - write : off static indicator mode: off static indicator register: (s1, s0) = (0, 0) shl select: 0 d isplay start line: 0 (first) column address: 0 page address: 0 regulator resis tor select register: (r2, r1, r0) = (0, 0, 0) reference voltage set: off reference voltage control register: ( s v5, s v4, s v3, s v2, s v1, s v0) = (1, 0, 0, 0, 0, 0) while resetb is ?l? or reset instruction is executed, no instruction except read status can b e accepted. reset status appears at db4. after db4 becomes ?l?, any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before us ed.
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 34 instruction descript ion table 18 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read stat us 0 1 busy adc on /off res etb 0 0 0 0 read the internal status display on / off 0 0 1 0 1 0 1 1 1 d on turn on/off lcd panel when d on = 0: display off when d on = 1: display on initial display line 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 specify ddram line for com 1 set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 set r eference v oltage mode set r eference v oltage r egister 0 0 s v5 s v4 s v3 s v2 s v1 s v0 set r eference v oltage r egister set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 y7 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc = 0 : normal direction (seg1 ? seg132) when a dc = 1 : reverse dir ection (seg132 ? seg1) reverse display on / off 0 0 1 0 1 0 0 1 1 rev select normal / reverse display when rev = 0 : normal display when rev = 1 : reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal / entire display on when eon = 0 : normal display. when eon = 1 : entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset modify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode reset 0 0 1 1 1 0 0 0 1 0 ini tialize the internal functions shl select 0 0 1 1 0 0 shl select com output direction when shl = 0 : normal direction (com1 ? com64) when shl = 1: reverse direction (com64 ? com1) power control 0 0 0 0 1 0 1 vc vr vf control power circuit op eration regulator resistor select 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator mode set static indicator register 0 0 s1 s0 set static i ndicator register power s ave - - - - - - - - - - compound instruction of display off and entire display on test instruction 0 0 1 1 1 1 don't use this instruction. ? x ? : don ? t care
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 35 read display data 8 - bit data from d isplay d ata ram specified b y the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8 - bit data of d isplay d ata from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 26 . sequence for writing display data figure 27 . sequence for reading display data
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 36 read stat u s indicates the internal status of the s6b1713. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on / off res etb 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram column address and segment dri ver. 0: reverse direction (seg 132 ? seg 1 ), 1: normal direction (seg 1 ? seg 132 ) on / off indicates display on / off status 0: display on, 1: display off res etb indicates the initialization is in progress by resetb signal. 0: chip is active, 1: chip is bei ng reset. display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off initial display line sets the line address of display ram to determine the i nitial d isplay l ine . the ram display data is displayed at the top row (com 1 when shl = l, com64 when shl = h ) of lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 l ine address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 37 r eference voltage select consists of 2 - byte instruction the 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st i nstruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd i nstruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 sv5 s v4 s v3 s v2 s v1 s v 0 s v5 s v4 s v3 s v2 s v1 s v0 reference voltage pa rameter ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 28 . sequence for setting the r eference v oltage
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 38 s et page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age a ddress and column address are specified. along with the column address, the p age a ddress defines the address of th e display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 set colu mn address sets the c olumn a ddress of display ram from the microprocessor into the c olumn a ddress register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor read s or writes display data to or from display ram, column addresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 y7 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 39 adc select changes the relationship between ram column address and segment driver. the direction of se gment driver output pins can be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 1 ? seg 132 ) adc = 1: reverse direction (seg 132 ? seg 1 ) r everse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illum inated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of th e display data ram are held. this instruction has priority over the reverse display on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal di splay eon = 1: e ntire di splay o n select lcd bias selects lcd bias ra tio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 b ias lcd bias d uty r atio d uty 1 d uty0 b ias = 0 bias = 1 1/33 0 0 1/ 5 1/6 1/49 0 1 1/ 6 1/8 1/65 1 0 /1 1/ 7 1/9
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 40 set modify - read this instruct ion stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is rep eatedly changed during cursor blinking or others. this mode is canceled by the reset modify - read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify - read this instruction cancels the modify - read mode, and makes the column address return to its initial value just before the set modify - read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no yes change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 29 . sequence for cursor display
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 41 reset this instruction resets initi al display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 1 ? com 64 ) shl = 1: reverse direction (com 64 ? com 1 ) power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal vo ltage follower circuit is on
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 42 regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. r efer to the t able 15 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 1 + ( rb / ra ) 0 0 0 1.9 0 0 0 1 2.19 0 1 0 2.55 0 1 1 3.02 1 0 0 3.61 1 0 1 4.35 1 1 0 5.29 1 1 1 6.48 set static indicator state consists of two bytes instruction. the first byte instruction (set static indicator mode) enables the second byte instruction (set static indicator r egister) to be valid. the first byte sets the static indicator on / off. when it is on, the second byte updates the contents of static indicator register without issuing any other i nstruction and this static indicator state is released after setting the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1 : static indicator on the 2 nd instruction: set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 1 second blinking) 1 0 on (about 0.5 second blinking ) 1 1 on (always on)
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 43 power save ( c ompound i nstruction) if the entire display on / off instruction is issued during the display off state, s6b1713 enters the p ower s ave status to reduce the power consumption to the static power consumption value. accordi ng to the status of static indicator mode, power save is entered to one of two modes (sleep and standby mode). when s tatic i ndicator mode is on, standby mode is issued, when off, sleep mode is issued. power save mode is released by the display on and entir e display off instruction. release standby mode power save off (compound instruction) [entire display off] [display on] release sleep mode power save off (compound instruction) [entire display off] [static indicator on] [display on] pow er save (compound instruction) [display off] [entire display on] static indicator off static indicator o n sleep m ode [oscillator c ircuit: off] [lcd power s upply c ircuit: off] [all com / seg o utputs: v ss ] [consumption c urrent: < 2 m a] standby mode [oscillator c ircuit: on] [lcd power s upply c ircuit: off] [all com/seg o utputs: v ss ] [consumption c urrent: < 10 m a] figure 30 . power save routine
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 44 referential i nstruction s etup f low (1) end of initialization waiting for stabilizing the lcd power levels user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) with keeping the resetb pin = ? l ? user system setup by external pins turn on the voltage converter by internal instructions [power control: vc=1, vr=0, vf=0] turn on the voltage regulator by internal instructions [power control: vc=1, vr=1, vf=0] turn on the voltage follower by internal instructions [power control: vc=1, vr=1, vf=1] set the lcd operating voltage by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for 50% rising of vout waiting for 3 1ms figure 31 . initializing with the b uilt - in p ower s upply c ircuits
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 45 referential i nstruction s etup f low (2 ) user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power on ( v dd - v ss ) with keeping the resetb pin = ? l ? user system setup by external pins set power save release power save set the lcd operating voltage by internal instructions [regulator r esistor s elect] [reference voltage r egister s et] waiting for stabilizing the lcd power levels end of initialization figure 32 . initializing without the b uilt - in p ower s upply c ircuits
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 46 referential i nstruction s etup f low (3) end of initialization write initial display data display data ram addressing by instruction [initial display line] [set page address] [set column address] end of data display turn display on by instruction [display o n /off: don=1] figure 33 . data d isplaying
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 47 referential i nstruction s etup f low (4) turn display off by instruction [display on/o ff : don=0] optional status power off (v dd - v ss ) turn off the voltage follower by internal instructions [power control: vc=1, vr=0, vf=0] turn off the voltage regulator by internal instructions [power control: vc=1, vr=0, vf=1] turn off the voltage converter by internal instructions [power control: vc=0, vr=0, vf=0] waiting for 3 50ms waiting for 3 1ms waiting for 3 1ms figure 34 . power o ff
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 48 specifications absolute maximum rat ings table 19. absolute maximum ratings parameter symbol rating unit v dd - 0.3 to +7.0 v supply voltage range v lcd - 0.3 to + 17 .0 v input voltage range v in - 0.3 to v dd +0.3 v operating temperature range t opr - 40 to +85 c storage temperature range t str - 55 to +125 c notes: 1. vdd and vlcd are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. (vlcd = v0 ? vss) 3. if supply voltage exceeds its abso lute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 49 dc characteris tics table 20. dc characteristics (v ss = 0v, v dd = 2.4 to 5.5 v, ta = - 40 to 85 c) item symbol condition min. typ. max unit pin used operating voltage (1) v dd select by product code 2.4 - 5.5 v v dd *1 operating voltage (2) v0 4.0 - 1 5 .0 v v0 *2 high v ih 0.8v dd - v dd input vo ltage low v il v ss - 0.2v dd v *3 high v oh i oh = - 0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v dd = 3.0 v v in = v dd or v ss - 1.0 - + 1.0 m a * 5 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a * 6 lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn * 7 internal f osc 17 22 27 oscillator frequency (1) external f cl v dd = 3.0v ta = 25 c duty ratio = 1/65, 1/33 4.25 5.50 6.75 khz cl *8 internal f osc 20 2 5 30 oscill ator frequency (2) external f cl v dd = 3.0v ta = 25 c duty ratio = 1/49 3.33 4.17 5.00 k hz cl *8 2 2.4 - 5.5 3 2.4 - 5.0 4 2.4 - 3.75 voltage converter input voltage v dd 5 2.4 - 3. 0 v v dd voltage converte r output voltage vout 2 / 3 / 4 / 5 voltage conversion (no - load ) 95 99 - % vout voltage regulator operating voltage vout 4 .0 - 1 5 .0 v vout voltage follower operating voltage v0 4.0 - 1 5 .0 v v0 * 9 v ref 0 - 0.0 5%/ c 1.94 2.00 2.06 v * 10 reference voltage v ref 1 v dd = 3.0 v ta = 25 c - 0.2%/ c 1.94 2.00 2.06 v * 10
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 50 dynamic current consumption (1) when the b uilt - in power c ircuit is off (at o perate m ode) (ta = 25 c ) item symbol condition min. typ. max. unit pin used dynamic current consumption (1) i dd1 v dd = 3.0v v0 ? v ss = 11.0v 1/65 du ty ratio display p attern off - - 20 m a *11 dynamic current consumption (2) when t he built - in power circuit is on (at operate mode) (ta = 25 c ) item symbol condition min. typ. max. unit pin used v dd = 3.0v, quad boosting, v0 ? v ss = 11.0v, 1/65 duty ratio, display pattern off, normal power mode - 70 100 m a *1 2 dynamic current con sumption (2) i dd2 v dd = 3.0v, quad boosting, v0 ? v ss = 11.0v, 1/65 duty ratio, display pattern checker, normal power mode - 95 160 m a * 1 2 current consumption during power save m ode (ta = 25 c ) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 v dd = 3.0v during s leep - - 2.0 m a standby mode current i dd s 2 v dd = 3.0v during st andby - - 10.0 m a
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 51 table 21 . t he relationship between oscillation frequency and frame frequency duty ratio i tem f cl f m on - chip oscillator circuit is used f osc ? ? ? ? 4 f osc ? ? ? ? 8 65 1/ 65 on - chip oscillator circuit is not used external input (f cl ) f cl ? ? ? ? 2 65 on - chip oscillator circuit is used f osc ? ? ? ? 6 f osc ? ? ? ? 12 49 1/49 on - chip oscillator circuit is not used external input (f cl ) f cl ? ? ? ? 2 49 on - chip oscillator circuit is used f osc ? ? ? ? 8 f osc ? ? ? ? 16 33 1/33 on - chip oscillator circuit is not used ex ternal input (f cl ) f cl ? ? ? ? 2 33 (f osc : oscillation frequency, f cl : display clock frequency, f m : lcd ac signal frequency ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, ms, mi , ps, intrs, hpm, temps , bsts , dcdc5b, cls, cl, m, disp pins . *4 . db0 to db7, m , frs, disp, cl pins . *5 . cs1b, cs2, rs, db [7:0], e_rd, rw_wr, resetb, ms, mi, ps, intrs, hpm, temps, bsts , dcdc5b, cls, cl, m, disp pins. *6 . applies when the db [7:0], m, disp, and cl pins are in high impedance. *7 . resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. ron= d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) *8 . see t able 21 for the relationship between oscillation frequency and frame frequency. *9 . the voltage regulator circuit a djusts v0 within the voltage follower operating voltage range *10 . on - chip reference voltage source of the voltage regulator circuit to adjust v0. *11,12. applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built - in power supply circuit is on or off. the current flowing through voltage regulation resistors (ra and rb) is not included. it does not include the current of the lcd panel capac ity, wiring capacity, etc.
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 52 reference data i dd1 vs. v dd * test c ondition: temperature: 25 c & 85 c, v0 = 11v (external), temps = 'l', 1/65 duty, normal power mode v dd vs. i dd1 (pattern off) 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd1 [ua] 11.0v, 1/65 duty (25c) 11.0v, 1/65 duty (85c) figure 35. display pattern is o ff
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 53 i dd2 vs. v dd * test c ondition : temperature: 25 c & 85 c, 1/65 duty, quad b oosting , rr = 6, ev = 32 v dd vs. i dd2 (pattern off) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 v dd [v] i dd2 [ua] 1/65 duty (25c) 1/65 duty (85c) figure 36. display pattern is o ff v dd vs. i dd2 (checker pattern) 0.00 20.00 40.00 60.00 80.00 100.00 120.00 140.00 160.00 180.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 v dd [v] i dd2 [ua] 1/65 duty (25c) 1/65 duty (85c) figure 37. display pattern is checker
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 54 ac characteristics read / write characteristics (8080 - serie s mpu) db 0 to db 7 (write) db 0 to db 7 (read) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw l 80(r) , t pw l 80(w) t cy80 t ah80 t as80 / rd, / wr cs1b ( cs2 ) rs t pw h 80(r) , t pw h 80(w) ** t pwl80(w) and t pwl80(r) is specified in the overlapped period when cs1b is low (cs2 is high) and /wr(/rd) is low. figure 38. read / write characteristics (8080 - series mpu)
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 55 (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as80 t ah80 13 17 - - ns system cycle time /wr, /rd t cy80 400 - - ns read t pw l 80 (r) 125 - - ns enable pulse low width write / wr , /rd t pw l 80 (w) 55 - - ns read t pw h 80 (r) 245 - - ns enable pulse high width write / wr , /rd t pw h 80 (w) 315 - - ns data se tup time data hold time t ds80 t dh80 35 13 - - ns read access time output disable time db7 to db0 t acc80 t od80 - 10 - 125 90 ns c l = 100 pf (v dd = 4.5 to 5.5 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as80 t ah80 10 10 - - ns system cycle time /wr, /rd t cy80 160 - - ns read t pw l 80 (r) 65 - - ns enable pulse low width write / wr , /rd t pw l 80 (w) 25 - - ns read t pw h 80 (r) 65 - - ns enable pulse high width write / wr , /rd t pw h 80 (w) 105 - - ns data setup time data hold time t ds80 t dh80 18 10 - - ns read access time output disable time db7 to db0 t acc80 t od80 - 10 - 65 45 ns c l = 100 pf note the input signal rising time and falling time (tr, tf) is specified at 15ns or less . or (tr + tf) < (t cy80 ? t pwl80 (w) ? t pwh80 (w) ) for write, (tr + tf) < (t cy80 ? t pwl80 (r) ? t pwh80 (r) ) for read
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 56 r ead / write characteristics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw h 68(r) , t pw h 68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e cs1b ( cs2 ) rs ,rw db 0 to db 7 (read) t pw l 68(r) , t pw l 68(w) ** t pwh68(w) and t pwh68(r) is specified in the overlapped period when cs1b is low (cs2 is high) and e is high. figure 39. read / write characteristics (68 00 - series microprocessor)
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 57 (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs ,rw t as68 t ah68 13 17 - - ns system cycle time e t cy68 400 - - ns read t pw l 68 (r) 125 - - enable p ulse low w idth write e t pw l 68 (w) 55 - - ns read t pw h 68 (r) 245 - - enable p ulse high w idth write e t pw h 68 (w) 315 - - ns data setup time data hold time t ds68 t dh68 35 13 - - ns access time output disable time db7 to db0 t acc68 t od68 - 10 - 125 90 ns c l = 100 pf (v dd = 4.5 to 5.5 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs ,rw t as68 t ah68 10 10 - - ns system cycle time e t cy68 160 - - ns read t pw l 68 (r) 65 - - enable p ul se low w idth write e t pw l 68 (w) 25 - - ns read t pw h 68 (r) 65 - - enable p ulse high w idth write e t pw h 68 (w) 105 - - ns data setup time data hold time t ds68 t dh68 18 10 - - ns access time output disable time db7 to db0 t acc68 t od68 - 10 - 65 45 ns c l = 100 pf note: 1. the input signal rising time and falling time (tr, tf) is specified at 15ns or less . or (tr + tf) < (t cy68 ? t pwl68 (w) ? t pwh68 (w) ) for write, (tr + tf) < (t cy68 ? t pwl68 (r) ? t pwh68 (r) ) for read .
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 58 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 ) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 40. serial interface characteristics (v dd = 2.4 to 3 . 6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 4 50 1 8 0 1 35 - - - - - - ns address setup time address hold time rs t ass t ahs 90 360 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 90 9 0 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 5 5 1 8 0 - - - - ns (v dd = 4.5 to 5.5 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cys t whs t wls 225 90 70 - - - - - - ns address setup time address hold time r s t ass t ahs 45 180 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 45 45 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 25 90 - - - - ns
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 59 reset input timing resetb t rw figure 41. reset input timing (v dd = 2. 4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 9 00 - - ns (v dd = 4.5 to 5.5 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 450 - - ns display control output timing t dm cl m figure 42. display control output timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark m d elay t ime m t dm - 13 70 ns (v dd = 4.5 to 5.5 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark m d elay t ime m t dm - 10 35 ns
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 60 reference applicatio ns microprocessor inter face in case of interfacing with 6800 - series (ps = ?h?, mi = ?h?) db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb mi ps s 6b1 7 13 figure 43. i nterfacing with 6800 - se ries (ps = ?h?, mi = ?h?) in case of interfacing with 8080 - series (ps = ?h?, mi = ?l?) db0 to db7 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb mi ps s 6b1 71 3 figure 44. i nterfacing with 8080 - series (ps = ?h?, mi = ?l?) in case of serial interface (ps = ?l?, mi = ?h/l?) open resetb v ss v dd or v ss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 mi ps s 6b1 71 3 f igure 45. s erial i nterface (ps = ?l?, mi = ?h/l?)
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 61 connections between s6b1713 and lcd pane l single chip configuration (1/ 6 5 duty configurations) coms com64 : com33 com32 : com1 coms seg1 ........... seg132 s 6b1 713 ( bottom view ) ? a x a ? a x a 64 132 pixels com32 : com1 coms coms com64 : com33 seg132 ........... seg1 s 6b1 713 ( top view ) 64 132 pixels ? a x a ? a x a figure 46 . shl = 0, adc = 0 figure 47 . shl = 0, adc = 1 com33 : com64 coms coms com1 : com32 seg1 ........... seg132 s 6b1 713 ( top view ) com33 : com64 coms coms com1 : com32 seg132 ............ seg1 s 6b1 713 ( bottom view ) ? a x a ? a x a 64 132 pixels ? a x a ? a x a 64 132 pixels figure 48 . shl = 1, adc = 0 figure 49 . shl = 1, adc = 1
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 62 single chip configuration (1/ 49 duty configurations) coms com64 : com 41 com 24 : com1 coms seg1 ........... seg132 s 6b1 713 ( bottom view ) ? a x a ? a x a 48 132 pixels com 24 : com1 coms coms com64 : com 41 seg132 ........... seg1 s 6b1 713 ( top view ) 48 132 pixels ? a x a ? a x a figure 50 . shl = 0, adc = 0 figure 51 . shl = 0, adc = 1 com 41 : com64 coms coms com1 : com 24 seg1 ........... seg132 s 6b1 713 ( top view ) com 41 : com64 coms coms com1 : com 24 seg132 ............ seg1 s 6b1 713 ( bottom view ) ? a x a ? a x a 48 132 pixels ? a x a ? a x a 48 132 pixels figure 52 . shl = 1, adc = 0 figure 53 . shl = 1, adc = 1
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 63 single chip configuration (1/ 33 duty configurations) coms com64 : com 49 com 16 : com1 coms seg1 ........... seg132 s 6b1 713 ( bottom view ) ? a x a ? a x a 32 132 pixels com 16 : com1 coms coms com64 : com 49 seg132 ........... seg1 s 6b1 713 ( top view ) 32 132 pixels ? a x a ? a x a figure 54 . shl = 0, adc = 0 figure 55 . shl = 0, adc = 1 com 49 : com64 coms coms com1 : com 16 seg1 ........... seg132 s 6b1 713 ( top view ) com 49 : com64 coms coms com1 : com 16 seg132 ............ seg1 s 6b1 713 ( bottom view ) ? a x a ? a x a 32 132 pixels ? a x a ? a x a 32 132 pixels figure 56 . shl = 1, adc = 0 figure 57 . shl = 1, adc = 1
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 64 mu l ti ple c hip configuration - 65com (64com + 1coms) 264seg (132seg 2) ? a x a ? a x a 64 264 pixels com s com 64 : com 33 com 32 : com 1 com s seg 1 ............... seg1 32 s 6b1 713 ( bottom view ) ( master ) com s com 64 : com 33 com 32 : com 1 com s seg1 ............... seg1 32 s 6b1 713 ( bottom view ) ( slave ) figure 58 . shl = 0, adc = 0 connect th e following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 com s com 1 : com 32 com 33 : com 64 com s seg1 32 ................. seg1 s 6b1 713 ( bottom view ) ( master ) com s com 1 : com 32 com 33 : com 64 com s seg1 32 ................. seg1 s 6b1 713 ( bottom view ) ( slave ) ? a x a ? a x a 64 264 pixels figure 59 . shl = 1, adc = 1 connect the following pins of two c hips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4
s6b1713 6 5 com / 1 32 se g driver & controlle r for stn lcd 65 - 130com (128com + 2coms) 132seg coms com64 : com33 com32 : com1 coms seg1 ................. seg132 s 6b1 713 ( bottom view ) ( slave ) com s com 1 : com 32 com 33 : com 64 com s seg1 32 ................. seg1 s 6b1 713 ( bottom view ) ( master ) ? a x a ? a x a 128 132 pixels figure 60. 130com ( 1 28com + 2coms) 132seg connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 common / segment output direction select - master c hip: shl = 1, adc = 1 - slave c hip: shl = 0, ad c = 0
65 com / 1 32 seg driver & contro ller for stn lcd s6b1713 66 tcp pin layout (samp le) s6b1713 (top view) frs m cl disp cs1b cs2 resetb rs rw_wr e_rd db0 db1 db2 db3 db4 db5 db6 db7 duty0 duty1 ms cls mi ps v ss v dd vout c3+ c3- c1+ c1- c2+ c2- vr v0 v1 v2 v3 v4 bsts dcdc5b hpm intrs temps com33 com34 com35 : : : com46 com47 com48 : : : com62 com63 com64 coms seg132 seg131 seg130 seg129 : : : : seg66 seg65 seg64 seg63 : : : : seg4 seg3 seg2 seg1 com32 com31 com30 : : : com17 com16 com15 : : : com3 com2 com1 coms figure 61. tcp pin layout

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